ASIC Design Verification (block, subsystem, and full SoC levels) Strong SystemVerilog + UVM/OVM (testbench architecture, sequences, coverage) Develop verification plans, test strategies, and coverage models from specs Constrained random verification, assertions, and functional coverage Debug complex issues using waveform analysis and root-cause methodologies Experience with large, complex SoCs (AI, GPU, HPC, networking) Integration and use of 3rd-party Verification IP (VIP) Perform code coverage and functional coverage closure Strong RTL understanding (Verilog/SystemVerilog ) for design validation Experience with processor architectures (ARM, MIPS, RISC-V) Familiarity with AMBA protocols (AXI, AHB, APB) and SoC interfaces Exposure to high-speed interfaces (PCIe, Ethernet, DDR, USB, SPI, I2C) Scripting for automation (Python, Perl, Tcl, Bash ) Experience supporting lab bring-up, silicon validation, and post-silicon debug Knowledge of ASIC flows/tools (lint, LEC, STA, synthesis, PnR awareness) #J-18808-Ljbffr
Asic Design Verification / Validation Engineer (Intermediate, Senior, Principal Levels)
MYTICAS CONSULTING
ottawa, ottawa
Published 27 days ago
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