Position : Analog Layout EngineerExperience : 5 to 15 YearsLocation : Ottawa, CanadaJob Type : Full-Time / PermanentWork Model : OnsiteRole OverviewWe are seeking a skilledAnalog Layout Engineerwith strong hands-on experience inadvanced nodes (TSMC 3nm or 5nm)to join our layout design team inCanada . The ideal candidate will have a solid background in the layout of analog and mixed-signal circuits for high-performance SoCs and IPs. Key ResponsibilitiesExecute full custom layout ofanalog and mixed-signal blocks(e.g., op-amps, bandgaps, comparators, LDOs, PLLs, data converters)Participate in floorplanning, placement, routing, and optimization of analog blocksDrive layout closure with designers acrossmultiple PVT cornersEnsure compliance withDRC, LVS, ERC, and EM/IR requirementsCollaborate with circuit designers to address layout-dependent effects (LDE), parasitic extraction (PEX), and performance-sensitive layoutDeliver layout forTSMC 3nm/5nm technologies , meeting aggressive area, power, and performance goalsRequired Skills5+ years of experience inanalog/mixed-signal layoutHands-on experience with TSMC 5nm or 3nm process nodesProficient in usingCadence Virtuosolayout tools (XL/GXL)Strong understanding ofmatching ,shielding ,parasitics , and analog layout best practicesExperience withPEX (Parasitic Extraction)andpost-layout simulation collaborationFamiliarity withCalibre/Assurafor DRC, LVS, and physical verificationGood to HaveExperience withEM/IR analysis tools(e.g., Voltus-Fi)Scripting skills (Skill, Python, or Tcl)Background inlayout automation techniquesExposure to high-speed layout (SerDes, DDR, PLLs)Why Join UsOpportunity to work on leading-edge3nm/5nm analog IPsCollaborative work environment with exposure toworld-class SoC teamsCompetitive compensation and career growth path#J-18808-Ljbffr