Senior Digital Design Engineer Build and lead digital development and design projects for high‑speed integrated circuits. Lead and manage digital development and design projects. Responsible for all aspects of digital blocks and ICs development from initial concept, architecture and specification through to final verification. Oversee all phases of the design cycle—specification, modeling, RTL, verification, synthesis, timing closure, vector generation and simulation, lab testing, layout support and documentation. Plan, lead and execute incremental updates and maintenance of existing digital designs, test systems, and supporting software and scripts. Conduct and contribute to design reviews, provide input to characterization and qualification test systems, and support backend design targeting silicon, FPGAs and system simulators. Qualifications BSc or MSc in Electronic Engineering or Computer Engineering. 3–6 years of digital IC design experience (academic work considered). Experience in VHDL and/or Verilog design and simulation. Front‑end tool experience (Synopsys, Cadence, Mentor) and flow experience—including verification, simulators, synthesis, STA, back‑annotation and gate‑level simulation. Experience with backend tools, flow, floor‑planning or coordination with the backend team. Experience with DSP algorithms and building blocks is a strong plus. Hands‑on experience with scripting (csh, Tcl/Tk, Perl, etc.). Ability to work with global, cross‑functional teams. Project management skills are a plus. Good analytical and debugging skills. Highly motivated and independent. Excellent command of English verbal and written communication skills. Perks and Benefits Competitive compensation. Great work environment. Hybrid work eligibility. Only candidates with multiple IC tape‑outs will be considered. SerDes / Analog Mixed‑Signal IC Design Engineer Design and validate analog and mixed‑signal integrated circuits. Qualifications We’re Seeking Minimum of a Master’s or PhD in Electrical Engineering with a focus on IC design. 3+ years of design experience, including CTLE, DFE, ADC, DAC, oscillators, PLLs, and more. SerDes or high‑speed circuit design (10 GS/s) experience. Multiple silicon designs taped out with measured results. Experience in SOI or FinFET process nodes. Comfortable with scripting, programming, Matlab/Simulink and Python. Excellent communication, presentation skills, and a strong team player. Strong preference for candidates eligible to work in Canada. Perks and Benefits Competitive compensation. Great work environment. Hybrid work eligibility. Only applicants with multiple IC tape‑outs will be considered. Principal Silicon Photonics / Analog / Mixed‑Signal Design Engineer Lead design of TIA and driver blocks for silicon photonics applications, integrating active circuits with photonics elements into high‑speed electro‑optical systems. Qualifications We’re Seeking Minimum of a Master’s or PhD in Electrical Engineering with a focus on IC design. 3+ years in design, including optical front‑end receivers and transmitters, CTLE, DFE, ADC, DAC, oscillators, PLLs, etc. Experience with photonics design (PD, MRM, MZ elements). High‑speed circuit design ( Multiple silicon designs taped out with measured results. Co‑design and co‑simulation of photonics and electronics experience. Experience in SOI or FinFET process nodes. Comfortable with scripting, programming, MATLAB/Simulink and Python. Excellent communication, presentation skills, and a strong team player. Strong preference for candidates eligible to work in Canada. Perks and Benefits Competitive compensation. Great work environment. Hybrid work eligibility. Only applicants with multiple IC tape‑outs will be considered. Principal Project Manager Manage high‑speed ASIC design projects from initial design through customer delivery. Required Experience 5+ years of project management experience in high‑speed ASIC design. Managing multiple mixed‑signal projects from initial design to customer delivery. Collaboration with design teams and all stakeholders. Extensive schedule and project management experience using Agile/scrum flow with proven on‑time delivery. Perks and Benefits Competitive compensation. Great work environment. Hybrid work eligibility. Only applicants with multiple IC tape‑outs will be considered. Senior Physical Design / Layout Engineer Develop and expand the physical design team, focusing on analog and mixed‑signal layout. Key Responsibilities Design layouts for key analog/mixed‑signal designs. Perform EMIR, DFM, parasitic analysis and optimization. Collaborate with analog/mixed‑signal and digital designers on layout and floor‑plans. Project management and task delegation. Create and manage scripts for flow optimization. Contribute to design flow. Manage on‑site and off‑site resources. Discuss and transfer knowledge with clients on layout/floor‑plan requirements. Qualifications Minimum Bachelors in Electrical or Computer Engineering. 3+ years of experience. Multiple tape‑out experience in advanced technology nodes. High‑speed layout experience is a significant asset. SOI or FinFET experience is a significant asset. Experience in Cadence design flow. Strong communication skills and ability to work well in a team environment. Benefits Competitive compensation. Great work environment. Hybrid work eligibility. Remote working for Canadian applications. Only candidates with multiple IC tape‑outs will be considered. #J-18808-Ljbffr