We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self‑driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high‑performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with deep expertise in high‑speed serial communication and transceiver design, blending theoretical rigor with hands‑on laboratory proficiency. You thrive in dynamic, cross‑disciplinary environments, collaborating with analog, digital, and hardware teams to realize innovative solutions. Your background includes advanced modeling, signal processing, and hardware validation, making you a pivotal contributor to projects involving PCIe and Ethernet protocols. You have a natural inclination for mentoring, guiding junior engineers, and sharing your technical wisdom. Your analytical mindset and attention to detail help you anticipate challenges and craft robust architectures. As an adaptable problem solver, you excel at troubleshooting complex systems and supporting customers through technical challenges. You are passionate about advancing connectivity technologies and are eager to lead simulation and sign‑off activities that ensure best‑in‑class product reliability. With your strong communication skills, you foster transparency and alignment across teams, and your commitment to excellence drives Synopsys’ continued leadership in high‑performance connectivity solutions. You are motivated by opportunities to innovate, empower others, and make a tangible impact on next‑generation silicon products. What You’ll Be Doing: Collaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage. Developing and maintaining comprehensive simulation and verification plans for IP, aligning with reliability and performance targets. Reviewing execution against verification plans through regular meetings with multiple verification teams (analog, cosim, DV, GLS, formal, emulation). Establishing, monitoring, and reporting on key verification metrics such as functional, code, and assertion coverage. Coordinating with Firmware & Algorithms Lead and Digital FW Developers to develop hardware regression plans for successive FW releases. Delivering high‑quality verification collateral including test plans, test cases, coverage reports, and sign‑off documentation. What You’ll Need: MSc or PhD in Electrical/Computer Engineering, with 10+ years of relevant industry experience. Deep expertise in high‑speed protocols—PCIe and Ethernet. Proficiency in SystemVerilog, object‑oriented verification, UVM/VMM/OVM, and assertion‑based verification, coverage closure expertise. Strong scripting/programming: Python, TCL, Perl, C/C++. In‑depth knowledge of high‑speed analog and digital design principles. Familiarity with verification flows: analog, co‑simulation, digital verification, GLS, formal methods, and emulation. Proven leadership: testbench architecture, planning, cross‑site collaboration, and mentoring. Who You Are: Innovative and forward‑thinking, always seeking new solutions to technical challenges. Detail‑oriented, with a rigorous approach to analysis and validation. Collaborative and effective in cross‑functional team settings. Strong communicator and mentor, able to share knowledge and guide others. Adaptable, thriving in fast‑paced and evolving environments. Customer‑focused, dedicated to delivering high‑quality support and solutions. The Impact You Will Have: Advance high‑speed connectivity for enterprise and hyperscale applications worldwide. Ensure robust and scalable solutions for a diverse global customer base. Drive innovation in SerDes design, modeling, and validation methodologies. Accelerate time‑to‑market for cutting‑edge silicon products. Empower customers by delivering expert technical support and troubleshooting. Strengthen Synopsys’ reputation as an industry leader in high‑performance connectivity IP. Enable successful silicon implementation by catching issues early through rigorous simulation and verification. Facilitate cross‑team collaboration that enhances product quality and reliability. The Team You’ll Be a Part Of: You’ll join a world‑class engineering team focused on developing, verifying, and delivering industry‑leading high‑speed connectivity IP. Our team is a blend of domain experts in analog and digital design, modeling, and hardware validation, working collaboratively to push boundaries in SerDes and transceiver technologies. Together, we drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications. #J-18808-Ljbffr