Commitment: Full-time preferred; high availability required (40 hours)Duration: Target engagement of ~3+ monthsLocation: Remote, USA and Canada onlyRTL Design Engineer Qualifications3-10 years of experience in digital RTL designStrong proficiency in Verilog / SystemVerilogSolid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocolsExperience with ASIC design flows: lint, synthesis, timing analysis, CDC, DFT-aware designFamiliarity with common EDA tools for simulation, waveform debug, lint, CDC, synthesis, timing analysisFamiliarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflowsAbility to write clear design documentation and communicate technical tradeoffsExperience debugging RTL issues using simulation logs and waveform viewersStrong collaboration skills across architecture, verification, and implementation teamsPreferredAMBA protocols (AXI, AHB, APB)Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power designExposure to formal verification or SV/UVM-based design verificationDesign Verification Engineer Qualifications3-10 years of experience in design verificationStrong proficiency in SystemVerilog and UVMSolid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocolsExperience developing reusable verification components and testbench infrastructureConstrained-random verification, functional coverage, assertions (SVA), coverage closureFamiliarity with EDA tools for simulation, waveform debug, coverage analysis, formal verification, regression managementFamiliarity with LLM-based tools to accelerate verification, debug, test generation, documentation, or coverage analysisAbility to write clear verification plans, debug reports, and technical documentationPreferredAMBA protocols (AXI, AHB, APB)Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power verificationReusable verification IP, scoreboards, reference models, coverage-driven regression flows#J-18808-Ljbffr