A leading company in digital technology is seeking a Senior Design Verification Engineer to enhance high-performance data communication systems. The role involves reviewing design specifications, leading verification tasks, and collaborating with cross-functional teams. Candidates should have strong skills in SystemVerilog and UVM, with a focus on advanced semiconductor projects in a supportive work culture.#J-18808-Ljbffr
Senior Verification Engineer - Systemverilog/Uvm, Serdes
TALENTLAB
toronto, toronto
Published 27 days ago
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