Role Overview We are seeking a highly experienced Architect specializing in high‑speed SerDes design with deep expertise in advanced analog/mixed‑signal circuits, XSR (Extra‑Short‑Reach) interfaces, and optical I/O technologies. In this role, you will provide technical leadership across complex, next‑generation PHY architectures, driving innovation from concept through production. You will work with cross‑functional teams and influence strategic direction across product lines while solving highly complex design challenges in advanced process nodes. Key Responsibilities Advanced SerDes Architecture Lead the architectural definition of the E224+ SerDes, including identifying required modifications to meet customer‑driven performance, power, and latency targets. Architect and specify high‑performance analog front‑ends, including CTLE/DFE, TX FIR filters, PLLs/CDRs, ADC/DAC‑based architectures, and clocking subsystems. Updated channel modeling assumptions VSR‑specific equalization strategies AFE re‑partitioning and optimization Clocking improvements and tighter jitter budgets Lead feasibility analysis and modeling of next‑generation SerDes channels, including electrical, XSR, and optical interconnect environments. Drive innovation in optical I/O, including modulator/driver integration, TIAs, and photonics‑electrical co‑design workflows. Technical problem‑solving leading debug of complex silicon issues spanning analog, digital, packaging, and optical domains. Develop innovative solutions to challenging PHY‑level problems using deep expertise in circuits, channel modeling, and system behavior. Partner with cross‑disciplinary teams to contribute to long‑term technology strategy in SerDes, chiplets, and optical‑interconnect domains that are aligned to industry trends. Analog & Mixed‑Signal Design Define and guide development of critical analog building blocks: CTLE, DFE, slicers High‑speed TX drivers and VSR‑tuned FIR tap structures CDR/PLL architectures supporting sub‑ps jitter ADC/DAC‑based receive architectures, if applicable Optimize AFE and receiver signal chains for VSR channels, extremely low reach, and tighter insertion‑loss budgets. Guide design teams through detailed analog/mixed‑signal design, circuit partitioning, performance optimization, and silicon validation strategy. Review and approve block‑level and top‑level designs, ensuring alignment to architectural intent and performance targets. Collaborate with layout, modeling, signal‑integrity, packaging, and system teams to optimize end‑to‑end performance and power. Required Qualifications 15+ years of experience in analog/mixed‑signal circuit design, SerDes PHYs, or related high‑speed I/O. Proven track record architecting multi‑generation SerDes PHYs, preferably at 56G+, 112G+, or 224G+. Deep expertise in analog building blocks: LNAs, TIAs, CTLE, DFE, TX drivers, PLL/CDR, ADC/DAC‑based SerDes. Hands‑on silicon bring‑up experience in SerDes or high‑speed analog designs. Experience working with foundries on advanced process nodes (e.g., 5nm, 3nm). Skilled in simulation/verification (Spice, AMS), modeling (Matlab/Simulink, Verilog‑A), and lab measurement methodologies. Hands‑on knowledge of XSR/USR interfaces and chiplet‑based architectures.Demonstrated ability to lead large, cross‑functional technical initiatives with minimal oversight. Preferred Qualifications Experience with DSP equalization, MLSD, or nonlinear cancellation for 224G+ operation. Experience with optical links, co‑packaged optics, optical modulators, drivers, and photonics integration a strong asset. Strong understanding of signal integrity, channel modeling, equalization techniques, and advanced packaging (2.5D/3D, interposers). Publications, patents, or industry recognition in high‑speed I/O or optical domains. Ability to mentor senior designers and uplift organizational technical capability. #J-18808-Ljbffr