Principal SerDes System/DSP Design Engineer As the global leader in high‑speed connectivity, Ciena is committed to a people‑first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well‑being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute Lead the design and development of electrical SerDes DSP architectures for high‑speed data communication systems. Perform system‑level evaluation, modeling, and performance analysis of SerDes transceiver solutions including impairments and mitigation techniques. Develop algorithms and architectures for adaptive equalization, maximum likelihood sequence detection (MLSD), and timing recovery algorithms. Integrate control theory and advanced DSP designs into feasible hardware implementations. Collaborate with cross‑functional teams (analog design, ASIC design, electro‑optical hardware, firmware) to optimize SerDes performance in end‑to‑end systems. Conduct design trade‑offs to meet stringent performance, power, and area targets. Analyze channel models, analog circuits impairments (DAC, ADC, AFE, …) and system constraints to determine system‑level margin and FEC (forward error correction) performance and optimize system margin. Provide system‑level specifications for different sub‑blocks of SerDes transceivers such as DAC, ADC, AFE, PLL. Evaluate and model IMDD optical links and formulate strategies to enhance system robustness. Document design specifications, system performance results, and contribute to IP generation and innovation roadmaps. Must Haves Advanced expertise in electrical SerDes DSP design and implementation. Proven experience in SerDes system‑level evaluation, modeling, and simulation. Strong proficiency in control theory and digital signal processing (DSP) applied to high‑speed communication systems. Familiarity with optical IMDD (Intensity Modulation Direct Detection) systems. Deep understanding of adaptive equalization techniques for high‑speed links. Proficiency with maximum likelihood sequence detection (MLSD) approaches. Expertise in timing recovery schemes in high‑speed serial links. Practical knowledge of FEC performance modeling and system‑level performance optimization. Experience with MATLAB, Python, or C/C++ for algorithm design and simulation. Strong problem‑solving skills and ability to work across hardware/software boundaries. Ph.D. in Electrical Engineering with background in digital communications and signal processing. 8+ years of experience in high‑speed serial link or communication system design. Nice To Haves Knowledge of industry standards such as PCIe, IEEE, Ethernet, or OIF standards for optical communication. Hands‑on experience with lab bring‑up, characterization, and debugging of SerDes links. Pay Range The annual salary range is $126,100 - $201,500 CAD. Benefits In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(k) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. #J-18808-Ljbffr