Position : Analog Layout EngineerExperience : 5 to 15 YearsLocation : Ottawa, CanadaJob Type : Full-Time / PermanentWork Model : OnsiteRole Overview We are seeking a skilled Analog Layout Engineer with strong hands-on experience in advanced nodes (TSMC 3nm or 5nm) to join our layout design team in Canada . The ideal candidate will have a solid background in the layout of analog and mixed-signal circuits for high-performance SoCs and IPs. Key Responsibilities Execute full custom layout of analog and mixed-signal blocks (e.g., op-amps, bandgaps, comparators, LDOs, PLLs, data converters) Participate in floorplanning, placement, routing, and optimization of analog blocks Drive layout closure with designers across multiple PVT corners Ensure compliance with DRC, LVS, ERC, and EM/IR requirements Collaborate with circuit designers to address layout-dependent effects (LDE), parasitic extraction (PEX), and performance-sensitive layout Deliver layout for TSMC 3nm/5nm technologies , meeting aggressive area, power, and performance goals Required Skills 5+ years of experience in analog/mixed-signal layout Hands-on experience with TSMC 5nm or 3nm process nodes Proficient in using Cadence Virtuoso layout tools (XL/GXL) Strong understanding of matching , shielding , parasitics , and analog layout best practices Experience with PEX (Parasitic Extraction) and post-layout simulation collaboration Familiarity with Calibre/Assura for DRC, LVS, and physical verification Good to Have Experience with EM/IR analysis tools (e.g., Voltus-Fi) Scripting skills (Skill, Python, or Tcl) Background in layout automation techniques Exposure to high-speed layout (SerDes, DDR, PLLs) Why Join Us Opportunity to work on leading-edge 3nm/5nm analog IPs Collaborative work environment with exposure to world-class SoC teams Competitive compensation and career growth path #J-18808-Ljbffr