Senior FPGA Architect / Principal FPGA Engineer – Real-Time Processing Systems Architect-level FPGA expertise designing high-performance real-time processing systems and complex programmable logic architectures. Advanced RTL development using Verilog / SystemVerilog for high-throughput pipelines, accelerators, and timing-sensitive hardware logic. Experience building FPGA-based SoC architectures including AXI/Avalon fabrics, DMA engines, memory controllers, and multi-clock domain designs. Strong background in high-bandwidth data-path design , resource utilization optimization, timing feasibility, and device architecture trade-offs. Hands‑on expertise with Xilinx UltraScale+/MPSoC and/or Intel FPGA families (Arria, Stratix, Agilex) and associated development toolchains. Deep experience integrating high-speed interfaces such as PCIe, Ethernet, and high-speed serial transceivers (SERDES). Familiarity with video/media transport or other latency-sensitive real-time processing environments involving high data throughput. Proven ability to drive timing closure, synthesis, floorplanning, constraint management, and place‑and‑route optimization . Strong verification leadership including simulation‑driven validation, UVM environments, constrained‑random testing, and coverage‑driven methodologies. Practical lab experience performing FPGA bring‑up, system integration, and hardware debug using scopes, logic analyzers, and embedded debug tools. Comfortable collaborating across hardware, software, and verification teams to deliver integrated high-performance systems. Demonstrated technical leadership and mentorship , guiding architecture decisions, design reviews, and engineering best practices. #J-18808-Ljbffr