FPGA Design Verification (DVT) across block, subsystem, and system levels StrongSystemVerilog + UVM(testbench architecture, stimulus, coverage) RTL understanding (Verilog/SystemVerilog) with ability to validate against specs Developverification plans, test strategies, and coverage modelsfrom architecture Executefunctional, integration, regression, and negative testing Debug complex issues usingwaveform analysis, root-cause, expected vs actual Experience withhigh-speed interfaces(PCIe, Ethernet, DDR, SPI, I2C, USB) Exposure totelecom/wireless (4G, LTE, 5G, O-RAN, 3GPP)environments Knowledge ofasynchronous clock domains & timing considerations Hands-on withsimulation, regression frameworks, and coverage analysis tools Scripting for automation ( Python, Tcl, Bash ) and CI/CD integration Experience withXilinx Vivado or Intel Quartus (Agilex)toolchains Lab bring-up, hardware validation, andsystem-level troubleshooting Ability to identifygaps, ambiguities, and edge casesin requirements Strong collaboration with design teams; supportsdesign-for-verification (DFV)#J-18808-Ljbffr
Fpga Design Verification (Dvt) Engineers (Int, Senior And Prinicipal)
MYTICAS CONSULTING
ahuntsic north, ahuntsic north
Published 26 days ago
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